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authorSebastian Kuzminsky <seb@highlab.com>2016-02-29 09:23:42 -0700
committerSebastian Kuzminsky <seb@highlab.com>2016-04-04 11:50:33 -0600
commit5f5881b35f90256d5fe4a6ffed93aa86956267f8 (patch)
tree59c7d36250e50ebd9db378c880500595f9ccbe9b /debian/control
parent48afb5dab1492a3f283522e469faeaa9cb1d7623 (diff)
add yosys-doc
Include the "manual" and "presentation" pdfs in yosys-doc.deb. Don't compress the pdf docs.
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diff --git a/debian/control b/debian/control
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+++ b/debian/control
@@ -48,3 +48,19 @@ Description: Framework for Verilog RTL synthesis
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
+
+Package: yosys-doc
+Section: doc
+Architecture: all
+Depends: ${misc:Depends}
+Suggests: yosys
+Description: Documentation for Yosys
+ Yosys is a framework for Verilog RTL synthesis. It currently has extensive
+ Verilog-2005 support and provides a basic set of synthesis algorithms for
+ various application domains.
+ .
+ Yosys can be adapted to perform any synthesis job by combining the existing
+ passes (algorithms) using synthesis scripts and adding additional passes as
+ needed by extending the yosys C++ code base.
+ .
+ This package contains the manual.