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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2014-04-12 22:07:08 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2014-04-12 22:07:08 +0200 |
| commit | bd69c2380c56d6fe7651686c9768ce09cafe4452 (patch) | |
| tree | fef2fedf006d66c43b43ffa8b21a4c4a63086b30 /debian/control | |
| parent | f65a2e63f18071f02f8e9ade7e1eda978ea0e85b (diff) | |
Now it builds under pbuilder chroot environment
Diffstat (limited to 'debian/control')
| -rw-r--r-- | debian/control | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debian/control b/debian/control index 1e1d4d87..1a5dd26b 100644 --- a/debian/control +++ b/debian/control @@ -2,13 +2,13 @@ Source: yosys Section: universe/electronics Priority: extra Maintainer: Ruben Undheim <ruben.undheim@gmail.com> -Build-Depends: debhelper (>= 9), tcl8.5-dev, libqt4-dev +Build-Depends: debhelper (>= 9), tcl8.5-dev, libqt4-dev, libqt4-opengl-dev, libqtwebkit-dev, libreadline-dev, git, zlib1g-dev, bison, flex, mercurial, iverilog, minisat Standards-Version: 3.9.2 Homepage: http://www.clifford.at/yosys #Vcs-Git: https://github.com/cliffordwolf/yosys.git Package: yosys Architecture: any -Depends: ${shlibs:Depends}, ${misc:Depends} +Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz Description: Open source synthesis of digital circuits yosys is a complete package for the synthesis from RTL to gate-level logic. |