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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-06 05:36:20 +0000 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-06 05:36:20 +0000 |
| commit | 64c3781bce4ed3102e73fdc2cc026fbb5d59c737 (patch) | |
| tree | ab77e17657b11223e01d481eca2c0aa5e79e45d9 /debian/control | |
| parent | fb1d2327b51c1653b733b81db6ca8edf92e14503 (diff) | |
Updated copyright file
Diffstat (limited to 'debian/control')
| -rw-r--r-- | debian/control | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/debian/control b/debian/control index c6a729e2..4ec6f577 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,8 @@ Source: yosys Section: electronics Priority: optional Maintainer: Ruben Undheim <ruben.undheim@gmail.com> -Build-Depends: debhelper (>= 9), tcl8.5-dev, libqt4-dev, libqt4-opengl-dev, libqtwebkit-dev, libreadline-dev, git, zlib1g-dev, bison, flex, iverilog, minisat +Build-Depends: debhelper (>= 9), tcl8.5-dev, libreadline-dev, git, bison, + flex, gawk, libffi-dev Standards-Version: 3.9.5 Vcs-Git: git://github.com/rubund/yosys.git -b debian Vcs-Browser: https://github.com/rubund/yosys/tree/debian @@ -10,7 +11,7 @@ Homepage: http://www.clifford.at/yosys Package: yosys Architecture: any -Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz +Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz, xdot Recommends: abc Description: Open source synthesis of digital circuits yosys is a complete package for the synthesis from RTL to gate-level logic. |