summaryrefslogtreecommitdiff
path: root/debian/control
diff options
context:
space:
mode:
authorRuben Undheim <ruben.undheim@gmail.com>2014-09-14 10:31:33 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2014-09-14 10:31:33 +0200
commit74e38fa5c5d11cb21f853d101cdda57e9f0424b8 (patch)
treead55afc58c99af07a993c0c7413c9dd5f6b07f37 /debian/control
parent6a45d5ad37ef45720db597f66caefd8ffd1684b3 (diff)
Not starting description with package name
Diffstat (limited to 'debian/control')
-rw-r--r--debian/control2
1 files changed, 1 insertions, 1 deletions
diff --git a/debian/control b/debian/control
index 6d296588..66738746 100644
--- a/debian/control
+++ b/debian/control
@@ -13,7 +13,7 @@ Package: yosys
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz, xdot,
berkeley-abc
-Description: Yosys Open SYnthesis Suite
+Description: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.