diff options
| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-11 11:48:54 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-11 13:35:05 +0200 |
| commit | 09963d6ddd745b07cac61c25d78d202e4d7043fd (patch) | |
| tree | d56dcf20d9aa547f96640cf15dc417b73f5530d7 /debian/control | |
| parent | 5a2c6845cfbc4cdb3ed73fcf7dadeea72fb35a4f (diff) | |
Some updates to the packaging:
* debian/copyright:
- Use https protocol in Format field
* debian/control:
- Added dh-python as build-dependency (Closes: #896802)
- Changed VCS URLs to Salsa
- Mark 'yosys-doc' Multi-Arch: foreign
- Remove 'Testsuite: autopkgtest' since it is now handled automatically
- Updated Standards Version to 4.1.5 - requires reproducability
* debian/patches/0007-Disable-pretty-build.patch:
- New patch to disable pretty build (Closes: #847110)
* debian/rules:
- Upstream source has moved to https://github.com/YosysHQ/yosys
Diffstat (limited to 'debian/control')
| -rw-r--r-- | debian/control | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/debian/control b/debian/control index 17aa0e2e..e18ca98a 100644 --- a/debian/control +++ b/debian/control @@ -4,8 +4,8 @@ Uploaders: Ruben Undheim <ruben.undheim@gmail.com>, Sebastian Kuzminsky <seb@highlab.com> Section: electronics Priority: optional -Testsuite: autopkgtest Build-Depends: debhelper (>= 9), + dh-python, tcl-dev, libreadline-dev, bison, @@ -30,9 +30,9 @@ Build-Depends-Indep: texlive-bibtex-extra, lmodern, graphviz -Standards-Version: 3.9.8 -Vcs-Browser: https://anonscm.debian.org/cgit/debian-science/packages/yosys.git -Vcs-Git: https://anonscm.debian.org/git/debian-science/packages/yosys.git +Standards-Version: 4.1.5 +Vcs-Browser: https://salsa.debian.org/science-team/yosys +Vcs-Git: https://salsa.debian.org/science-team/yosys.git Homepage: http://www.clifford.at/yosys Package: yosys @@ -71,6 +71,7 @@ Package: yosys-doc Section: doc Architecture: all Depends: ${misc:Depends} +Multi-Arch: foreign Suggests: yosys Description: Documentation for Yosys Yosys is a framework for Verilog RTL synthesis. It currently has extensive |