diff options
author | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-10 20:22:05 +0200 |
---|---|---|
committer | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-10 20:22:05 +0200 |
commit | 7177324393140277afe665d26d729e1589433454 (patch) | |
tree | 32a4254eee3c40194e262e05560a2df7fbaf6ef2 /debian/control | |
parent | 785ce0fe09f1a4325ff7a6659c71ac33351b8e8d (diff) |
Extended the description in d/control
Diffstat (limited to 'debian/control')
-rw-r--r-- | debian/control | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/debian/control b/debian/control index 4ec6f577..6f5129f6 100644 --- a/debian/control +++ b/debian/control @@ -13,5 +13,11 @@ Package: yosys Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz, xdot Recommends: abc -Description: Open source synthesis of digital circuits - yosys is a complete package for the synthesis from RTL to gate-level logic. +Description: Yosys Open SYnthesis Suite + Yosys is a framework for Verilog RTL synthesis. It currently has extensive + Verilog-2005 support and provides a basic set of synthesis algorithms for + various application domains. + . + Yosys can be adapted to perform any synthesis job by combining the existing + passes (algorithms) using synthesis scripts and adding additional passes as + needed by extending the yosys C++ code base. |