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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-17 18:18:09 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-17 18:18:46 +0200 |
| commit | 21b42cdffcb5b24bf467ecf2b74adea47bbdc393 (patch) | |
| tree | 5794a304e60e2060a34a6eaa076230c71de2001e /examples/basys3/example.xdc | |
| parent | 42942203476b47ac8ec62671e4c133b7c7fceab3 (diff) | |
| parent | 0b254e3191dbed4a29ee37c5ae7cfcf8d723fbb2 (diff) | |
Merge branch 'next'
Diffstat (limited to 'examples/basys3/example.xdc')
| -rw-r--r-- | examples/basys3/example.xdc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc index c1fd0e92..8cdaa199 100644 --- a/examples/basys3/example.xdc +++ b/examples/basys3/example.xdc @@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + |