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author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-17 18:18:09 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-17 18:18:46 +0200 |
commit | 21b42cdffcb5b24bf467ecf2b74adea47bbdc393 (patch) | |
tree | 5794a304e60e2060a34a6eaa076230c71de2001e /examples/intel/MAX10/runme_postsynth | |
parent | 42942203476b47ac8ec62671e4c133b7c7fceab3 (diff) | |
parent | 0b254e3191dbed4a29ee37c5ae7cfcf8d723fbb2 (diff) |
Merge branch 'next'
Diffstat (limited to 'examples/intel/MAX10/runme_postsynth')
-rw-r--r-- | examples/intel/MAX10/runme_postsynth | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/examples/intel/MAX10/runme_postsynth b/examples/intel/MAX10/runme_postsynth new file mode 100644 index 00000000..f1621054 --- /dev/null +++ b/examples/intel/MAX10/runme_postsynth @@ -0,0 +1,5 @@ +#!/bin/bash + +iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) +vvp -N verif_post + |