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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-17 18:18:09 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-17 18:18:46 +0200 |
| commit | 21b42cdffcb5b24bf467ecf2b74adea47bbdc393 (patch) | |
| tree | 5794a304e60e2060a34a6eaa076230c71de2001e /examples/intel/MAX10/top.v | |
| parent | 42942203476b47ac8ec62671e4c133b7c7fceab3 (diff) | |
| parent | 0b254e3191dbed4a29ee37c5ae7cfcf8d723fbb2 (diff) | |
Merge branch 'next'
Diffstat (limited to 'examples/intel/MAX10/top.v')
| -rw-r--r-- | examples/intel/MAX10/top.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/examples/intel/MAX10/top.v b/examples/intel/MAX10/top.v new file mode 100644 index 00000000..2bada0e2 --- /dev/null +++ b/examples/intel/MAX10/top.v @@ -0,0 +1,15 @@ +`default_nettype none +module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, + input wire [15:0] SW ); + + + sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); + sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); + sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); + sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2)); + sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0])); + sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); + sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); + sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); + +endmodule |