diff options
author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:22 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:22 +0200 |
commit | 78bfe0de96fa5c6a7e53689ef53deaeac1d0a7b8 (patch) | |
tree | cc36d8cc573f1e6cc9b15ccc85a66883356cbf5f /examples/osu035 | |
parent | 291bd6d9b3f51ea86c38bbe998c0896ad8b9fed2 (diff) | |
parent | 5033b51947a6ef02cb785b5622e993335efa750a (diff) |
Merge tag 'upstream/0.7+20180830git0b7a184'
Upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'examples/osu035')
-rw-r--r-- | examples/osu035/.gitignore | 3 | ||||
-rw-r--r-- | examples/osu035/Makefile | 13 | ||||
-rw-r--r-- | examples/osu035/example.constr | 2 | ||||
-rw-r--r-- | examples/osu035/example.v | 3 | ||||
-rw-r--r-- | examples/osu035/example.ys | 11 |
5 files changed, 32 insertions, 0 deletions
diff --git a/examples/osu035/.gitignore b/examples/osu035/.gitignore new file mode 100644 index 00000000..3abf340b --- /dev/null +++ b/examples/osu035/.gitignore @@ -0,0 +1,3 @@ +osu035_stdcells.lib +example.yslog +example.edif diff --git a/examples/osu035/Makefile b/examples/osu035/Makefile new file mode 100644 index 00000000..2bb8162b --- /dev/null +++ b/examples/osu035/Makefile @@ -0,0 +1,13 @@ + +example.edif: example.ys example.v example.constr osu035_stdcells.lib + yosys -l example.yslog -q example.ys + +osu035_stdcells.lib: + rm -f osu035_stdcells.lib.part osu035_stdcells.lib + wget -O osu035_stdcells.lib.part https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/ami035/signalstorm/osu035_stdcells.lib + mv osu035_stdcells.lib.part osu035_stdcells.lib + +clean: + rm -f osu035_stdcells.lib + rm -f example.yslog example.edif + diff --git a/examples/osu035/example.constr b/examples/osu035/example.constr new file mode 100644 index 00000000..eb2c6e8d --- /dev/null +++ b/examples/osu035/example.constr @@ -0,0 +1,2 @@ +set_driving_cell INVX1 +set_load 0.015 diff --git a/examples/osu035/example.v b/examples/osu035/example.v new file mode 100644 index 00000000..0f043e5f --- /dev/null +++ b/examples/osu035/example.v @@ -0,0 +1,3 @@ +module top (input clk, input [7:0] a, b, output reg [15:0] c); + always @(posedge clk) c <= a * b; +endmodule diff --git a/examples/osu035/example.ys b/examples/osu035/example.ys new file mode 100644 index 00000000..6821ef42 --- /dev/null +++ b/examples/osu035/example.ys @@ -0,0 +1,11 @@ +read_verilog example.v +read_liberty -lib osu035_stdcells.lib + +synth -top top + +dfflibmap -liberty osu035_stdcells.lib +abc -D 10000 -constr example.constr -liberty osu035_stdcells.lib +opt_clean + +stat -liberty osu035_stdcells.lib +write_edif example.edif |