diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 10:49:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 10:49:30 +0100 |
| commit | a8e9d37c14427527c9a810d83e183309cc5ca503 (patch) | |
| tree | 03f51c899b7f2b613e027de8610bd76f939dc076 /frontends/ast/ast.cc | |
| parent | 910556560fbf26df4f2960b7d94039a1f399f1a1 (diff) | |
Creating $meminit cells in verilog front-end
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 68b3327f..589b08e1 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -58,7 +58,7 @@ namespace AST_INTERNAL { std::map<std::string, AstNode*> current_scope; const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; - AstNode *current_top_block, *current_block, *current_block_child; + AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; } @@ -132,6 +132,7 @@ std::string AST::type2str(AstNodeType type) X(AST_TERNARY) X(AST_MEMRD) X(AST_MEMWR) + X(AST_MEMINIT) X(AST_TCALL) X(AST_ASSIGN) X(AST_CELL) |