diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 14:25:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 14:25:03 +0200 |
| commit | 27a872d1e7041be4894bc643a420587ff5894125 (patch) | |
| tree | 430d0411eaa4c4f6893576e2179d2eee93726def /frontends/ast/ast.h | |
| parent | 3c45277ee0f5822181c6058f679de632f834e7d2 (diff) | |
Added support for "upto" wires to Verilog front- and back-end
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 8253a205..6c15c03a 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -151,7 +151,7 @@ namespace AST // node content - most of it is unused in most node types std::string str; std::vector<RTLIL::State> bits; - bool is_input, is_output, is_reg, is_signed, is_string, range_valid; + bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped; int port_id, range_left, range_right; uint32_t integer; double realvalue; |