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authorClifford Wolf <clifford@clifford.at>2014-06-13 11:29:23 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-13 11:29:23 +0200
commit7ef0da32cdcddb50de8ba8acf0c6421fe5732c55 (patch)
tree66bdd2c13b6d54a44d9ac48f4971cf79e256356e /frontends/ast/ast.h
parent482d9208aa9dacb7afe21f08c882d4881581013a (diff)
Added Verilog lexer and parser support for real values
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r--frontends/ast/ast.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 802bf98f..aeb56e35 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -55,6 +55,7 @@ namespace AST
AST_ARGUMENT,
AST_RANGE,
AST_CONSTANT,
+ AST_REALVALUE,
AST_CELLTYPE,
AST_IDENTIFIER,
AST_PREFIX,
@@ -153,6 +154,7 @@ namespace AST
bool is_input, is_output, is_reg, is_signed, is_string, range_valid;
int port_id, range_left, range_right;
uint32_t integer;
+ double realvalue;
// this is set by simplify and used during RTLIL generation
AstNode *id2ast;