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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-13 13:59:13 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-13 13:59:13 +0100 |
| commit | cd9e8741a71502c303c6f25d02bb2259a7dd7ff3 (patch) | |
| tree | d7436b9dca95cb1eaec471c9e8d074dfa990bb27 /frontends/ast/ast.h | |
| parent | b4639078903847469c2cfe211b3e5d7006a78cc8 (diff) | |
Implemented read_verilog -defer
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 01702c3c..8335db09 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -232,7 +232,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false, bool defer = true); // parametric modules are supported directly by the AST library // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions |