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authorClifford Wolf <clifford@clifford.at>2013-08-19 20:58:01 +0200
committerClifford Wolf <clifford@clifford.at>2013-08-19 20:58:01 +0200
commit0003743432dc804f65e61253ee71883175693d86 (patch)
tree6e3a7c8322e02b644f24f5db48f23cc8587efcde /frontends/ast/genrtlil.cc
parent8656b1c08f34c3585ac8ec0e7285fbaaad6a7bc8 (diff)
Fixed width and sign detection for ** operator
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 50e95975..6ea07652 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -567,6 +567,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
case AST_SHIFT_RIGHT:
case AST_SHIFT_SLEFT:
case AST_SHIFT_SRIGHT:
+ case AST_POW:
children[0]->detectSignWidthWorker(width_hint, sign_hint);
break;
@@ -585,7 +586,6 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
case AST_MUL:
case AST_DIV:
case AST_MOD:
- case AST_POW:
for (auto child : children)
child->detectSignWidthWorker(width_hint, sign_hint);
break;
@@ -963,8 +963,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
- RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
- int width = std::max(left.width, right.width);
+ RTLIL::SigSpec right = type == AST_POW ? children[1]->genRTLIL() : children[1]->genRTLIL(width_hint, sign_hint);
+ int width = type == AST_POW ? left.width : std::max(left.width, right.width);
if (width > width_hint && width_hint > 0)
width = width_hint;
if (width < width_hint) {