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authorClifford Wolf <clifford@clifford.at>2014-01-29 00:59:28 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-29 00:59:28 +0100
commit375c4dddc19c7029b82d9d4482f32938b7f6cd85 (patch)
treea4be8f310eb12acd4adffa4075ada6c3ff4d7c89 /frontends/ast/genrtlil.cc
parenta86f33653d0b1b9ba09a118a29a2baf3bb0520a3 (diff)
Added read_verilog -icells option
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 83a5c750..6001e278 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1334,6 +1334,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
AstNode *child = *it;
if (child->type == AST_CELLTYPE) {
cell->type = child->str;
+ if (flag_icells && cell->type.substr(0, 2) == "\\$")
+ cell->type = cell->type.substr(1);
continue;
}
if (child->type == AST_PARASET) {