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authorClifford Wolf <clifford@clifford.at>2013-11-08 11:06:11 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-08 11:06:11 +0100
commit9f49d538e1e6bd59c848f19226c95949ba2f37b5 (patch)
tree6b47d7a4647d079a39f0cea581c8ff3c3c31964a /frontends/ast/simplify.cc
parentb04051a0e2f859c0d9f11109e8e05e9740438f9b (diff)
Fixed handling of different signedness in power operands
Diffstat (limited to 'frontends/ast/simplify.cc')
-rw-r--r--frontends/ast/simplify.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 9fa7f558..fdb6e9ed 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1020,7 +1020,7 @@ skip_dynamic_range_lvalue_expansion:;
if (0) { case AST_POW: const_func = RTLIL::const_pow; }
if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) {
RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint, sign_hint),
- RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? sign_hint : false, width_hint);
+ RTLIL::Const(children[1]->bits), sign_hint, type == AST_POW ? children[1]->is_signed : false, width_hint);
newNode = mkconst_bits(y.bits, sign_hint);
}
break;