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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:18:00 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:18:30 +0200
commit10e5791c5e5660cb784503d36439ee90d61eb06b (patch)
treed7bd3d8f1d0254e14fcf68ce25545f42afab9724 /frontends/ast
parentd088854b47f5f77c6a62be2ba4b895164938d7a2 (diff)
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'frontends/ast')
-rw-r--r--frontends/ast/ast.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 3f704bea..17041686 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -931,7 +931,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str = (*it)->str.substr(1);
if (defer)
(*it)->str = "$abstract" + (*it)->str;
- if (design->modules.count((*it)->str)) {
+ if (design->modules_.count((*it)->str)) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@@ -939,7 +939,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue;
}
- design->modules[(*it)->str] = process_module(*it, defer);
+ design->modules_[(*it)->str] = process_module(*it, defer);
}
}
@@ -1036,10 +1036,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
modname = "$paramod" + stripped_name + para_info;
}
- if (design->modules.count(modname) == 0) {
+ if (design->modules_.count(modname) == 0) {
new_ast->str = modname;
- design->modules[modname] = process_module(new_ast, false);
- design->modules[modname]->check();
+ design->modules_[modname] = process_module(new_ast, false);
+ design->modules_[modname]->check();
} else {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}