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authorClifford Wolf <clifford@clifford.at>2013-07-12 13:13:04 +0200
committerClifford Wolf <clifford@clifford.at>2013-07-12 13:13:04 +0200
commit3650fd7fbe45a00792770d9ecb9397bc27ea0845 (patch)
tree0ecf122082e664a9d2d7267bca5a17e8852fba62 /frontends/ast
parentded769c98cffe5682c0211dba08abc4a1efe3d5a (diff)
More fixes in ternary op sign handling
Diffstat (limited to 'frontends/ast')
-rw-r--r--frontends/ast/genrtlil.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index a9574254..e7ceec5f 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -998,6 +998,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate multiplexer for ternary operator (aka ?:-operator)
case AST_TERNARY:
{
+ if (width_hint < 0)
+ detectSignWidth(width_hint, sign_hint);
+
RTLIL::SigSpec cond = children[0]->genRTLIL();
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);