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authorClifford Wolf <clifford@clifford.at>2013-11-07 18:17:10 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-07 18:17:10 +0100
commit947bd9b96bb978e204275d6fbbc9ce9ff6eda28c (patch)
treec9f0f53390c6fdfba52d26a3571d761ef28449f9 /frontends/ast
parent0e1661f84e99f1d4a487e7a432b05a6cb2071714 (diff)
Renamed extend_un0() to extend_u0() and use it in genrtlil
Diffstat (limited to 'frontends/ast')
-rw-r--r--frontends/ast/genrtlil.cc12
1 files changed, 8 insertions, 4 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e901a3b5..c701c2fa 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -966,7 +966,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_TO_UNSIGNED: {
RTLIL::SigSpec sig = children[0]->genRTLIL();
if (sig.width < width_hint)
- sig.extend(width_hint, sign_hint);
+ sig.extend_u0(width_hint, sign_hint);
is_signed = sign_hint;
return sig;
}
@@ -983,7 +983,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
}
if (sig.width < width_hint)
- sig.extend(width_hint, false);
+ sig.extend_u0(width_hint, false);
return sig;
}
@@ -998,7 +998,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (int i = 0; i < count; i++)
sig.append(right);
if (sig.width < width_hint)
- sig.extend(width_hint, false);
+ sig.extend_u0(width_hint, false);
is_signed = false;
return sig;
}
@@ -1153,7 +1153,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed);
- return mux2rtlil(this, cond, val1, val2);
+ RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
+
+ if (sig.width < width_hint)
+ sig.extend_u0(width_hint, sign_hint);
+ return sig;
}
// generate $memrd cells for memory read ports