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authorRuben Undheim <ruben.undheim@gmail.com>2019-03-28 23:35:03 +0100
committerRuben Undheim <ruben.undheim@gmail.com>2019-03-28 23:35:03 +0100
commitff5734b20220e6fb4a3913cf5279ed94bb5156ea (patch)
tree4c438282926d7bac304ad3ad6ad89523c4c1d784 /frontends/ilang/ilang_parser.y
parentdb3c67fd6e140893450a44870ee9a75dd1f48b27 (diff)
Imported GIT HEAD: 0.8+20190328git32bd0f2
Diffstat (limited to 'frontends/ilang/ilang_parser.y')
-rw-r--r--frontends/ilang/ilang_parser.y42
1 files changed, 29 insertions, 13 deletions
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index bfc062fe..5bcc01f4 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -37,6 +37,8 @@ namespace ILANG_FRONTEND {
std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
std::vector<RTLIL::CaseRule*> case_stack;
dict<RTLIL::IdString, RTLIL::Const> attrbuf;
+ bool flag_nooverwrite, flag_overwrite;
+ bool delete_current_module;
}
using namespace ILANG_FRONTEND;
YOSYS_NAMESPACE_END
@@ -93,18 +95,36 @@ design:
module:
TOK_MODULE TOK_ID EOL {
- if (current_design->has($2))
- rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
+ delete_current_module = false;
+ if (current_design->has($2)) {
+ RTLIL::Module *existing_mod = current_design->module($2);
+ if (!flag_overwrite && attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()) {
+ log("Ignoring blackbox re-definition of module %s.\n", $2);
+ delete_current_module = true;
+ } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
+ } else if (flag_nooverwrite) {
+ log("Ignoring re-definition of module %s.\n", $2);
+ delete_current_module = true;
+ } else {
+ log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", $2);
+ current_design->remove(existing_mod);
+ }
+ }
current_module = new RTLIL::Module;
current_module->name = $2;
current_module->attributes = attrbuf;
- current_design->add(current_module);
+ if (!delete_current_module)
+ current_design->add(current_module);
attrbuf.clear();
free($2);
} module_body TOK_END {
if (attrbuf.size() != 0)
rtlil_frontend_ilang_yyerror("dangling attribute");
current_module->fixup_ports();
+ if (delete_current_module)
+ delete current_module;
+ current_module = nullptr;
} EOL;
module_body:
@@ -387,17 +407,13 @@ sigspec:
$$ = new RTLIL::SigSpec(current_module->wires_[$1]);
free($1);
} |
- TOK_ID '[' TOK_INT ']' {
- if (current_module->wires_.count($1) == 0)
- rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- $$ = new RTLIL::SigSpec(current_module->wires_[$1], $3);
- free($1);
+ sigspec '[' TOK_INT ']' {
+ $$ = new RTLIL::SigSpec($1->extract($3));
+ delete $1;
} |
- TOK_ID '[' TOK_INT ':' TOK_INT ']' {
- if (current_module->wires_.count($1) == 0)
- rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- $$ = new RTLIL::SigSpec(current_module->wires_[$1], $5, $3 - $5 + 1);
- free($1);
+ sigspec '[' TOK_INT ':' TOK_INT ']' {
+ $$ = new RTLIL::SigSpec($1->extract($5, $3 - $5 + 1));
+ delete $1;
} |
'{' sigspec_list '}' {
$$ = $2;