diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /frontends/liberty/liberty.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'frontends/liberty/liberty.cc')
| -rw-r--r-- | frontends/liberty/liberty.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 9000d702..c449a593 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -244,7 +244,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node) preset_sig = parse_func_expr(module, child->value.c_str()); } - if (clk_sig.width == 0 || data_sig.width == 0) + if (clk_sig.__width == 0 || data_sig.__width == 0) log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::id2cstr(module->name)); for (bool rerun_invert_rollback = true; rerun_invert_rollback;) @@ -284,21 +284,21 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node) cell->connections["\\C"] = clk_sig; module->add(cell); - if (clear_sig.width == 0 && preset_sig.width == 0) { + if (clear_sig.__width == 0 && preset_sig.__width == 0) { cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); } - if (clear_sig.width == 1 && preset_sig.width == 0) { + if (clear_sig.__width == 1 && preset_sig.__width == 0) { cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); cell->connections["\\R"] = clear_sig; } - if (clear_sig.width == 0 && preset_sig.width == 1) { + if (clear_sig.__width == 0 && preset_sig.__width == 1) { cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N'); cell->connections["\\R"] = preset_sig; } - if (clear_sig.width == 1 && preset_sig.width == 1) { + if (clear_sig.__width == 1 && preset_sig.__width == 1) { cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); cell->connections["\\S"] = preset_sig; cell->connections["\\R"] = clear_sig; @@ -326,7 +326,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node) preset_sig = parse_func_expr(module, child->value.c_str()); } - if (enable_sig.width == 0 || data_sig.width == 0) + if (enable_sig.__width == 0 || data_sig.__width == 0) log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::id2cstr(module->name)); for (bool rerun_invert_rollback = true; rerun_invert_rollback;) @@ -359,7 +359,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node) cell->connections["\\Y"] = iqn_sig; module->add(cell); - if (clear_sig.width == 1) + if (clear_sig.__width == 1) { RTLIL::SigSpec clear_negative = clear_sig; RTLIL::SigSpec clear_enable = clear_sig; @@ -396,7 +396,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node) module->add(enable_gate); } - if (preset_sig.width == 1) + if (preset_sig.__width == 1) { RTLIL::SigSpec preset_positive = preset_sig; RTLIL::SigSpec preset_enable = preset_sig; |