diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:35:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:35:06 +0200 |
| commit | 1d88f1cf9f2088de7825f5292db5b40d4f73d036 (patch) | |
| tree | ef1eeba2dcddbe957dabb8147b2b81cdc0d2ecd3 /frontends/liberty | |
| parent | 3cb61d03f8722fddfa14877accae1b3ca51e3926 (diff) | |
Removed deprecated module->new_wire()
Diffstat (limited to 'frontends/liberty')
| -rw-r--r-- | frontends/liberty/liberty.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index e7af9372..cf243f63 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -227,8 +227,8 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr) static void create_ff(RTLIL::Module *module, LibertyAst *node) { - RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0)))); - RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1)))); + RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0)))); + RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1)))); RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig; bool clk_polarity = true, clear_polarity = true, preset_polarity = true; @@ -309,8 +309,8 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node) static void create_latch(RTLIL::Module *module, LibertyAst *node) { - RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0)))); - RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1)))); + RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0)))); + RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1)))); RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig; bool enable_polarity = true, clear_polarity = true, preset_polarity = true; @@ -549,7 +549,7 @@ struct LibertyFrontend : public Frontend { } } if (!flag_lib || dir->value != "internal") - module->new_wire(1, RTLIL::escape_id(node->args.at(0))); + module->addWire(RTLIL::escape_id(node->args.at(0))); } for (auto node : cell->children) |