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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /frontends/liberty
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'frontends/liberty')
-rw-r--r--frontends/liberty/liberty.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index c476de87..0107b974 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -239,7 +239,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
{
rerun_invert_rollback = false;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (it.second->type == "$_INV_" && it.second->get("\\Y") == clk_sig) {
clk_sig = it.second->get("\\A");
clk_polarity = !clk_polarity;
@@ -316,7 +316,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
{
rerun_invert_rollback = false;
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
if (it.second->type == "$_INV_" && it.second->get("\\Y") == enable_sig) {
enable_sig = it.second->get("\\A");
enable_polarity = !enable_polarity;