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authorRuben Undheim <ruben.undheim@gmail.com>2018-10-17 17:59:38 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2018-10-17 17:59:38 +0200
commitdb3c67fd6e140893450a44870ee9a75dd1f48b27 (patch)
tree3d0e6c278632669b58dd2e69437333e06dba9b25 /frontends/verific
parent7b99a3646c44759b82d7df0361d59c72776b8aed (diff)
New upstream version 0.8
Diffstat (limited to 'frontends/verific')
-rw-r--r--frontends/verific/verific.cc18
1 files changed, 2 insertions, 16 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index dba3b0f0..c5fa5831 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -118,18 +118,6 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net)
return net_map.at(net);
}
-bool is_blackbox(Netlist *nl)
-{
- if (nl->IsBlackBox())
- return true;
-
- const char *attr = nl->GetAttValue("blackbox");
- if (attr != nullptr && strcmp(attr, "0"))
- return true;
-
- return false;
-}
-
void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
{
MapIter mi;
@@ -721,7 +709,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
netlist = nl;
if (design->has(module_name)) {
- if (!nl->IsOperator() && !is_blackbox(nl))
+ if (!nl->IsOperator())
log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
return;
}
@@ -730,7 +718,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
module->name = module_name;
design->add(module);
- if (is_blackbox(nl)) {
+ if (nl->IsBlackBox()) {
log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
module->set_bool_attribute("\\blackbox");
} else {
@@ -1688,7 +1676,6 @@ YOSYS_NAMESPACE_END
PRIVATE_NAMESPACE_BEGIN
-#ifdef YOSYS_ENABLE_VERIFIC
bool check_noverific_env()
{
const char *e = getenv("YOSYS_NOVERIFIC");
@@ -1698,7 +1685,6 @@ bool check_noverific_env()
return false;
return true;
}
-#endif
struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }