summaryrefslogtreecommitdiff
path: root/frontends/verilog/Makefile.inc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2015-01-08 00:05:11 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-08 00:05:11 +0100
commit38dfc5c580c8ba418783ec8cbee1a78c7cd5f788 (patch)
tree9683e27d3fbfee52ed01570bda8a7f2f1ed7fbee /frontends/verilog/Makefile.inc
parentfd787609aad5fcd7a817c4a7da0f6d89894c551a (diff)
added minimalistic xilinx sim models
Diffstat (limited to 'frontends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions