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authorClifford Wolf <clifford@clifford.at>2013-07-23 16:19:34 +0200
committerClifford Wolf <clifford@clifford.at>2013-07-23 16:19:34 +0200
commitad9bbcbf40451231178ccce67ab5aaff37da81da (patch)
treec35b9450a6ffe33d8388fb572fdcbc6a806bc0c5 /frontends/verilog/Makefile.inc
parentd815f1c77016a50a58260188283918c7aec958ae (diff)
Added $lut cells and abc lut mapping support
Diffstat (limited to 'frontends/verilog/Makefile.inc')
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