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authorClifford Wolf <clifford@clifford.at>2013-06-07 13:59:13 +0200
committerClifford Wolf <clifford@clifford.at>2013-06-07 13:59:13 +0200
commit46fbe9d26299a7b6197463b3056d778f525658fb (patch)
tree748b515d870f60b047e77e4b3e93257a116ccb46 /frontends/verilog/const2ast.cc
parent3371563f2f14ce0d6bc7798d0fc802b54aae93c8 (diff)
Added SAT generator and simple sat_solve command
Diffstat (limited to 'frontends/verilog/const2ast.cc')
-rw-r--r--frontends/verilog/const2ast.cc5
1 files changed, 2 insertions, 3 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index e5beaead..3a88fc04 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -186,12 +186,11 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
break;
default:
- goto error;
+ return NULL;
}
return AstNode::mkconst_bits(data, is_signed);
}
-error:
- log_error("Value conversion failed: `%s'\n", code.c_str());
+ return NULL;
}