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authorClifford Wolf <clifford@clifford.at>2014-01-19 04:18:22 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-19 04:18:22 +0100
commit9a1eb45c7517f224a2516ce235fd53d01d9ef908 (patch)
treebb049a5739784ba74c7574433cc0a7ab73d4b400 /frontends/verilog/lexer.l
parent3d7a1491aac0849a2a9fae2a06242e125de883d0 (diff)
Added Verilog parser support for asserts
Diffstat (limited to 'frontends/verilog/lexer.l')
-rw-r--r--frontends/verilog/lexer.l2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 9e606d90..81167cf4 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -113,6 +113,8 @@ namespace VERILOG_FRONTEND {
"generate" { return TOK_GENERATE; }
"endgenerate" { return TOK_ENDGENERATE; }
+"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; }
+
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }