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authorClifford Wolf <clifford@clifford.at>2014-06-06 17:40:04 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-06 17:40:04 +0200
commitb5cd7a01793294a53d91a2cd3ee9bbca5b9a8c54 (patch)
tree54118df8df6d0e9919c22cafb5a1cda924158633 /frontends/verilog/lexer.l
parentf9c1cd5edba5acb4d9b9dd287c7265111cf22087 (diff)
added while and repeat support to verilog parser
Diffstat (limited to 'frontends/verilog/lexer.l')
-rw-r--r--frontends/verilog/lexer.l2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 226a2670..5300d1b2 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -140,6 +140,8 @@ namespace VERILOG_FRONTEND {
"default" { return TOK_DEFAULT; }
"generate" { return TOK_GENERATE; }
"endgenerate" { return TOK_ENDGENERATE; }
+"while" { return TOK_WHILE; }
+"repeat" { return TOK_REPEAT; }
"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; }