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authorClifford Wolf <clifford@clifford.at>2014-02-17 14:28:52 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-17 14:28:52 +0100
commit02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9 (patch)
treee5adb1a2baa9eba28f7c28bf755d00da266bfe52 /frontends/verilog/parser.y
parent0851c2b6ea7044d9bce2014a2be2365a2bf7e1b0 (diff)
Added Verilog support for "`default_nettype none"
Diffstat (limited to 'frontends/verilog/parser.y')
-rw-r--r--frontends/verilog/parser.y1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 8080729b..4726f1aa 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -53,6 +53,7 @@ namespace VERILOG_FRONTEND {
struct AstNode *current_ast, *current_ast_mod;
int current_function_or_task_port_id;
std::vector<char> case_type_stack;
+ bool default_nettype_wire;
}
static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)