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authorClifford Wolf <clifford@clifford.at>2013-11-19 20:35:31 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-19 20:35:31 +0100
commit0dfdbd991afcbcc38110d22d489969ae33fb1f68 (patch)
treee30b5665c7ed0f0b43c5f7bcdb3b96b960165650 /frontends/verilog/parser.y
parent63285b300ca8a3057345f6b28ee20ff709ede24d (diff)
Fixed parsing of module arguments when one type is used for many args
Diffstat (limited to 'frontends/verilog/parser.y')
-rw-r--r--frontends/verilog/parser.y13
1 files changed, 10 insertions, 3 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 17f14d54..1dcc0d6c 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -248,9 +248,16 @@ optional_comma:
module_arg:
TOK_ID range {
- if (port_stubs.count(*$1) != 0)
- frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
- port_stubs[*$1] = ++port_counter;
+ if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
+ AstNode *node = ast_stack.back()->children.back()->clone();
+ node->str = *$1;
+ node->port_id = ++port_counter;
+ ast_stack.back()->children.push_back(node);
+ } else {
+ if (port_stubs.count(*$1) != 0)
+ frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
+ port_stubs[*$1] = ++port_counter;
+ }
if ($2 != NULL)
delete $2;
delete $1;