diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
commit | 02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9 (patch) | |
tree | e5adb1a2baa9eba28f7c28bf755d00da266bfe52 /frontends/verilog/verilog_frontend.cc | |
parent | 0851c2b6ea7044d9bce2014a2be2365a2bf7e1b0 (diff) |
Added Verilog support for "`default_nettype none"
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
-rw-r--r-- | frontends/verilog/verilog_frontend.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 477f26b4..13c2676d 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -256,6 +256,7 @@ struct VerilogFrontend : public Frontend { AST::get_line_num = &frontend_verilog_yyget_lineno; current_ast = new AST::AstNode(AST::AST_DESIGN); + default_nettype_wire = true; FILE *fp = f; std::string code_after_preproc; @@ -279,7 +280,7 @@ struct VerilogFrontend : public Frontend { child->attributes[attr] = AST::AstNode::mkconst_int(1, false); } - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); if (!flag_nopp) fclose(fp); |