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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:47:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:47:39 +0100 |
| commit | 1f1deda888ea32ade2478fca9fcb510ada477606 (patch) | |
| tree | bf21e5e60e970745af2d4652addfbe383f6b4187 /frontends/verilog/verilog_frontend.h | |
| parent | b005eedf369bc60ce5f7cba9a0db4694f22a360f (diff) | |
Added non-std verilog assume() statement
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
| -rw-r--r-- | frontends/verilog/verilog_frontend.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index e277f3e3..5561f54c 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -51,6 +51,9 @@ namespace VERILOG_FRONTEND // running in SystemVerilog mode extern bool sv_mode; + // running in -formal mode + extern bool formal_mode; + // lexer input stream extern std::istream *lexin; } |