diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-12-11 13:56:20 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-11 13:56:20 +0100 |
| commit | 1282a113da11351dbac2b9df53e3e430d12def4a (patch) | |
| tree | 161579a1c17417785fa2e389de991768ab99b3fd /frontends/verilog | |
| parent | 032511fac854cd0507dc84242bb55508c4757441 (diff) | |
Fixed supply0/supply1 with many wires
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 75af4652..621b6cc1 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -655,21 +655,33 @@ wire_decl: delete astbuf2; free_attr(albuf); } ';' | - attr TOK_SUPPLY0 TOK_ID ';' { + attr TOK_SUPPLY0 TOK_ID { ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); ast_stack.back()->children.back()->str = *$3; append_attr(ast_stack.back()->children.back(), $1); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1))); ast_stack.back()->children.back()->children[0]->str = *$3; delete $3; - } | - attr TOK_SUPPLY1 TOK_ID ';' { + } opt_supply_wires ';' | + attr TOK_SUPPLY1 TOK_ID { ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); ast_stack.back()->children.back()->str = *$3; append_attr(ast_stack.back()->children.back(), $1); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1))); ast_stack.back()->children.back()->children[0]->str = *$3; delete $3; + } opt_supply_wires ';'; + +opt_supply_wires: + /* empty */ | + opt_supply_wires ',' TOK_ID { + AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone(); + AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone(); + wire_node->str = *$3; + assign_node->children[0]->str = *$3; + ast_stack.back()->children.push_back(wire_node); + ast_stack.back()->children.push_back(assign_node); + delete $3; }; wire_name_list: |