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authorClifford Wolf <clifford@clifford.at>2014-07-31 13:19:47 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-31 13:19:47 +0200
commit1cb25c05b37b0172dbc50e140fe20f25d973dd8a (patch)
tree4bccb9f45ccad05346697c79afca9a1b21dced9c /frontends/verilog
parent1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (diff)
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Diffstat (limited to 'frontends/verilog')
-rw-r--r--frontends/verilog/const2ast.cc4
-rw-r--r--frontends/verilog/lexer.l3
-rw-r--r--frontends/verilog/parser.y7
-rw-r--r--frontends/verilog/preproc.cc4
-rw-r--r--frontends/verilog/verilog_frontend.cc3
-rw-r--r--frontends/verilog/verilog_frontend.h6
6 files changed, 24 insertions, 3 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 446f5e50..a81e3010 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -39,6 +39,8 @@
#include <string.h>
#include <math.h>
+YOSYS_NAMESPACE_BEGIN
+
using namespace AST;
// divide an arbitrary length decimal number by two and return the rest
@@ -210,3 +212,5 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
return NULL;
}
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 00deeb0b..fdb9bb02 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -44,13 +44,16 @@
#include "frontends/ast/ast.h"
#include "parser.tab.h"
+USING_YOSYS_NAMESPACE
using namespace AST;
using namespace VERILOG_FRONTEND;
+YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND {
std::vector<std::string> fn_stack;
std::vector<int> ln_stack;
}
+YOSYS_NAMESPACE_END
#define SV_KEYWORD(_tok) \
if (sv_mode) return _tok; \
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ce7b9927..c62e761e 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -39,9 +39,11 @@
#include "verilog_frontend.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
using namespace AST;
using namespace VERILOG_FRONTEND;
+YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND {
int port_counter;
std::map<std::string, int> port_stubs;
@@ -56,6 +58,7 @@ namespace VERILOG_FRONTEND {
bool default_nettype_wire;
bool sv_mode;
}
+YOSYS_NAMESPACE_END
static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
{
@@ -89,8 +92,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%union {
std::string *string;
- struct AstNode *ast;
- std::map<std::string, AstNode*> *al;
+ struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
+ std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
bool boolean;
}
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 2cfa8ca7..8efd4d7c 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -38,6 +38,8 @@
#include <stdio.h>
#include <string.h>
+YOSYS_NAMESPACE_BEGIN
+
static std::list<std::string> output_code;
static std::list<std::string> input_buffer;
static size_t input_buffer_charp;
@@ -427,3 +429,5 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
return output;
}
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index cbc594e8..4466e1cb 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -34,6 +34,7 @@
#include <sstream>
#include <stdarg.h>
+YOSYS_NAMESPACE_BEGIN
using namespace VERILOG_FRONTEND;
// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
@@ -376,3 +377,5 @@ struct VerilogDefaults : public Pass {
}
} VerilogDefaults;
+YOSYS_NAMESPACE_END
+
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 6d01a153..dac5b3d0 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -29,12 +29,14 @@
#ifndef VERILOG_FRONTEND_H
#define VERILOG_FRONTEND_H
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
#include "frontends/ast/ast.h"
#include <stdio.h>
#include <stdint.h>
#include <list>
+YOSYS_NAMESPACE_BEGIN
+
namespace VERILOG_FRONTEND
{
// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
@@ -53,6 +55,8 @@ namespace VERILOG_FRONTEND
// the pre-processor
std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs);
+YOSYS_NAMESPACE_END
+
// the usual bison/flex stuff
extern int frontend_verilog_yydebug;
int frontend_verilog_yylex(void);