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authorClifford Wolf <clifford@clifford.at>2014-08-21 12:42:28 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-21 12:42:28 +0200
commit38addd4c67905e3d1514ba839f07d94058e42560 (patch)
tree2c4a13cdfe523a6b460df75fbd0f863d97817087 /frontends/verilog
parenta92a68ce521c1e86c0666b9add0c88d59154325e (diff)
Added support for global tasks and functions
Diffstat (limited to 'frontends/verilog')
-rw-r--r--frontends/verilog/parser.y30
-rw-r--r--frontends/verilog/verilog_frontend.cc8
2 files changed, 23 insertions, 15 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index bf9b21bb..acd904e5 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -137,14 +137,21 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%%
-input:
- module input |
- defattr input |
- /* empty */ {
- for (auto &it : default_attr_list)
- delete it.second;
- default_attr_list.clear();
- };
+input: {
+ ast_stack.push_back(current_ast);
+} design {
+ ast_stack.pop_back();
+ log_assert(SIZE(ast_stack) == 0);
+ for (auto &it : default_attr_list)
+ delete it.second;
+ default_attr_list.clear();
+};
+
+design:
+ module design |
+ defattr design |
+ task_func_decl design |
+ /* empty */;
attr:
{
@@ -214,9 +221,9 @@ module:
attr TOK_MODULE TOK_ID {
do_not_require_port_stubs = false;
AstNode *mod = new AstNode(AST_MODULE);
- current_ast->children.push_back(mod);
- current_ast_mod = mod;
+ ast_stack.back()->children.push_back(mod);
ast_stack.push_back(mod);
+ current_ast_mod = mod;
port_stubs.clear();
port_counter = 0;
mod->str = *$3;
@@ -227,7 +234,8 @@ module:
frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str());
ast_stack.pop_back();
- log_assert(ast_stack.size() == 0);
+ log_assert(ast_stack.size() == 1);
+ current_ast_mod = NULL;
};
module_para_opt:
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 4466e1cb..19578908 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -285,10 +285,10 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yylex_destroy();
for (auto &child : current_ast->children) {
- log_assert(child->type == AST::AST_MODULE);
- for (auto &attr : attributes)
- if (child->attributes.count(attr) == 0)
- child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
+ if (child->type == AST::AST_MODULE)
+ for (auto &attr : attributes)
+ if (child->attributes.count(attr) == 0)
+ child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
}
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);