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authorClifford Wolf <clifford@clifford.at>2014-06-06 23:05:01 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-06 23:05:01 +0200
commit5281562d0e9468c584e6db6f30908e3155a76ad2 (patch)
treec7f3184ec25d2b1c45e5f635a1c7a889e29196e8 /frontends/verilog
parent76da2fe172ed6b0822a9e4a8cf9483ef7c8f5f40 (diff)
made the generate..endgenrate keywords optional
Diffstat (limited to 'frontends/verilog')
-rw-r--r--frontends/verilog/parser.y12
1 files changed, 8 insertions, 4 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index a12dcf14..42a8f91c 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -373,6 +373,8 @@ range_or_integer:
module_body:
module_body module_body_stmt |
+ /* the following line makes the generate..endgenrate keywords optional */
+ module_body gen_stmt |
/* empty */;
module_body_stmt:
@@ -1013,9 +1015,12 @@ single_arg:
};
module_gen_body:
- module_gen_body gen_stmt |
+ module_gen_body gen_stmt_or_module_body_stmt |
/* empty */;
+gen_stmt_or_module_body_stmt:
+ gen_stmt | module_body_stmt;
+
// this production creates the obligatory if-else shift/reduce conflict
gen_stmt:
TOK_FOR '(' {
@@ -1054,15 +1059,14 @@ gen_stmt:
if ($6 != NULL)
delete $6;
ast_stack.pop_back();
- } |
- module_body_stmt;
+ };
gen_stmt_block:
{
AstNode *node = new AstNode(AST_GENBLOCK);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
- } gen_stmt {
+ } gen_stmt_or_module_body_stmt {
ast_stack.pop_back();
};