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authorClifford Wolf <clifford@clifford.at>2013-03-31 11:17:56 +0200
committerClifford Wolf <clifford@clifford.at>2013-03-31 11:17:56 +0200
commit5640b7d6078a681e33e85f06920394204f41c875 (patch)
tree96ebae5ed0626ae5238fe8b794e50e0cb9d87e7c /frontends/verilog
parent04843bdcbeb62a202a6372ea5464de8c7ea66820 (diff)
Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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