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authorClifford Wolf <clifford@clifford.at>2013-08-15 21:00:06 +0200
committerClifford Wolf <clifford@clifford.at>2013-08-15 21:00:06 +0200
commita860efa8ac37dfe20cd74324dd02136082aa2c1c (patch)
tree699a9c13f5d9df33ae6de845134ed2f94dc8d8e4 /frontends/verilog
parent78658199e662979c8f9223be53b04c9d87a1d6f7 (diff)
Implemented same div-by-zero behavior as found in other synthesis tools
Diffstat (limited to 'frontends/verilog')
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