diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /frontends/vhdl2verilog/vhdl2verilog.cc | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
Fixed trailing whitespaces
Diffstat (limited to 'frontends/vhdl2verilog/vhdl2verilog.cc')
| -rw-r--r-- | frontends/vhdl2verilog/vhdl2verilog.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 82ff7b50..80bf243f 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -178,6 +178,6 @@ struct Vhdl2verilogPass : public Pass { log_pop(); } } Vhdl2verilogPass; - + YOSYS_NAMESPACE_END |