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authorClifford Wolf <clifford@clifford.at>2015-01-08 00:05:11 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-08 00:05:11 +0100
commit38dfc5c580c8ba418783ec8cbee1a78c7cd5f788 (patch)
tree9683e27d3fbfee52ed01570bda8a7f2f1ed7fbee /frontends/vhdl2verilog
parentfd787609aad5fcd7a817c4a7da0f6d89894c551a (diff)
added minimalistic xilinx sim models
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