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| author | Clifford Wolf <clifford@clifford.at> | 2015-11-26 18:24:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-11-26 18:24:23 +0100 |
| commit | a7ffb8569039736e041c92b272995159145430a6 (patch) | |
| tree | 6640f6af884c1b590ba1c44a1c70a62539a148d3 /frontends | |
| parent | 6459e3ac3965ea56c8e6fb1b4309a1258df778a7 (diff) | |
| parent | ab2d8e5c8cc78eb60f380fbdf5b09f2401ce27f6 (diff) | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e40f24cb..45cd4f3f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -314,6 +314,16 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, return true; } + if (inst->Type() == PRIM_DLATCHRS) + { + if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd()) + module->addDlatch(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); + else + module->addDlatchsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetSet()), net_map.at(inst->GetReset()), + net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); + return true; + } + #define IN operatorInput(inst, net_map) #define IN1 operatorInput1(inst, net_map) #define IN2 operatorInput2(inst, net_map) |