Another block of spelling fixes

Smaller this time

3 files changed, 7 insertions, 7 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index b93a53d2..a4585915 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -329,7 +329,7 @@ static std::string id2vl(std::string txt)
 	return txt;
 }
 
-// dump AST node as verilog pseudo-code
+// dump AST node as Verilog pseudo-code
 void AstNode::dumpVlog(FILE *f, std::string indent)
 {
 	bool first = true;
@@ -894,7 +894,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	AstNode *ast_before_simplify = ast->clone();
 
 	if (flag_dump_ast1) {
-		log("Dumping verilog AST before simplification:\n");
+		log("Dumping Verilog AST before simplification:\n");
 		ast->dumpAst(NULL, "    ");
 		log("--- END OF AST DUMP ---\n");
 	}
@@ -904,13 +904,13 @@ static AstModule* process_module(AstNode *ast, bool defer)
 		while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
 
 		if (flag_dump_ast2) {
-			log("Dumping verilog AST after simplification:\n");
+			log("Dumping Verilog AST after simplification:\n");
 			ast->dumpAst(NULL, "    ");
 			log("--- END OF AST DUMP ---\n");
 		}
 
 		if (flag_dump_vlog) {
-			log("Dumping verilog AST (as requested by dump_vlog option):\n");
+			log("Dumping Verilog AST (as requested by dump_vlog option):\n");
 			ast->dumpVlog(NULL, "    ");
 			log("--- END OF AST DUMP ---\n");
 		}
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index d54f1428..ebecb92f 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -136,7 +136,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 	}
 }
 
-// convert the verilog code for a constant to an AST node
+// convert the Verilog code for a constant to an AST node
 AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn_z)
 {
 	if (warn_z) {
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index bd7837b3..a7259358 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -281,7 +281,7 @@ supply1 { return TOK_SUPPLY1; }
 	static bool printed_warning = false;
 	if (!printed_warning) {
 		log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
-				"Yosys does support them but it is recommended to use verilog `full_case' attributes instead!\n");
+				"Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!\n");
 		printed_warning = true;
 	}
 	return TOK_SYNOPSYS_FULL_CASE;
@@ -290,7 +290,7 @@ supply1 { return TOK_SUPPLY1; }
 	static bool printed_warning = false;
 	if (!printed_warning) {
 		log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
-				"Yosys does support them but it is recommended to use verilog `parallel_case' attributes instead!\n");
+				"Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!\n");
 		printed_warning = true;
 	}
 	return TOK_SYNOPSYS_PARALLEL_CASE;