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authorClifford Wolf <clifford@clifford.at>2014-07-22 20:58:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:58:44 +0200
commit28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch)
tree9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /frontends
parent7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff)
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/genrtlil.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 34a3f1ba..a51064c3 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -311,7 +311,7 @@ struct AST_INTERNAL::ProcessGenerator
sig.optimize();
for (size_t i = 0; i < sig.chunks().size(); i++)
{
- RTLIL::SigChunk &chunk = sig.chunks()[i];
+ RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
if (chunk.wire == NULL)
continue;