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authorClifford Wolf <clifford@clifford.at>2013-11-22 15:01:12 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-22 15:01:12 +0100
commit295e352ba6aa1bd71431abc21a8f93735968cae6 (patch)
tree2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /frontends
parentc854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff)
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/ast.cc2
-rw-r--r--frontends/verilog/verilog_frontend.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 887ae85c..29093b83 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -720,7 +720,7 @@ static AstModule* process_module(AstNode *ast)
delete child;
}
ast->children.swap(new_children);
- ast->attributes["\\placeholder"] = AstNode::mkconst_int(1, false);
+ ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
}
ignoreThisSignalsInInitial = RTLIL::SigSpec();
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 1d26de73..1ef2f660 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -90,7 +90,7 @@ struct VerilogFrontend : public Frontend {
log(" do not run the pre-processor\n");
log("\n");
log(" -lib\n");
- log(" only create empty placeholder modules\n");
+ log(" only create empty blackbox modules\n");
log("\n");
log(" -noopt\n");
log(" don't perform basic optimizations (such as const folding) in the\n");