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authorClifford Wolf <clifford@clifford.at>2014-03-20 13:26:52 +0100
committerClifford Wolf <clifford@clifford.at>2014-03-20 13:26:52 +0100
commit470c2455e471318f4528da597e0dd8c7499b47ce (patch)
treeef6ea1e6e71d084fc312a4d3ab3244061da1b5f6 /frontends
parent9a34486bfbc8780d9a3af3164e99977e44d2a65f (diff)
Fixed mapping of Verific FADD primitive with unconnected outputs
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verific/verific.cc9
1 files changed, 5 insertions, 4 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1e15ef89..cf72b781 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -205,7 +205,8 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == PRIM_FADD)
{
RTLIL::SigSpec a = net_map.at(inst->GetInput1()), b = net_map.at(inst->GetInput2()), c = net_map.at(inst->GetCin());
- RTLIL::SigSpec x = net_map.at(inst->GetCout()), y = net_map.at(inst->GetOutput());
+ RTLIL::SigSpec x = inst->GetCout() ? net_map.at(inst->GetCout()) : module->new_wire(1, NEW_ID);
+ RTLIL::SigSpec y = inst->GetOutput() ? net_map.at(inst->GetOutput()) : module->new_wire(1, NEW_ID);
RTLIL::SigSpec tmp1 = module->new_wire(1, NEW_ID);
RTLIL::SigSpec tmp2 = module->new_wire(1, NEW_ID);
RTLIL::SigSpec tmp3 = module->new_wire(1, NEW_ID);
@@ -290,9 +291,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == PRIM_FADD)
{
RTLIL::SigSpec a_plus_b = module->new_wire(2, NEW_ID);
- RTLIL::SigSpec y = net_map.at(inst->GetOutput());
- y.append(net_map.at(inst->GetCout()));
-
+ RTLIL::SigSpec y = inst->GetOutput() ? net_map.at(inst->GetOutput()) : module->new_wire(1, NEW_ID);
+ if (inst->GetCout())
+ y.append(net_map.at(inst->GetCout()));
module->addAdd(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), a_plus_b);
module->addAdd(RTLIL::escape_id(inst->Name()), a_plus_b, net_map.at(inst->GetCin()), y);
return true;