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authorClifford Wolf <clifford@clifford.at>2013-12-05 12:53:49 +0100
committerClifford Wolf <clifford@clifford.at>2013-12-05 12:53:49 +0100
commit5c39948eadbcda58d0b880dc162572838dad01a2 (patch)
tree9b9559eb0fb352e776e7dd5984fac97d4bf20668 /frontends
parent853538d78b0207ca218524cb766fd5cdb165478d (diff)
Added AstNode::mkconst_str API
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/ast.cc17
-rw-r--r--frontends/ast/ast.h1
-rw-r--r--frontends/verilog/parser.y13
3 files changed, 19 insertions, 12 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 10c7fc85..7d5295a6 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -658,6 +658,23 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
return node;
}
+// create an AST node for a constant (using a string as value)
+AstNode *AstNode::mkconst_str(const std::string &str)
+{
+ std::vector<RTLIL::State> data;
+ data.reserve(str.size() * 8);
+ for (size_t i = 0; i < str.size(); i++) {
+ unsigned char ch = str[str.size() - i - 1];
+ for (int j = 0; j < 8; j++) {
+ data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
+ ch = ch >> 1;
+ }
+ }
+ AstNode *node = AstNode::mkconst_bits(data, false);
+ node->str = str;
+ return node;
+}
+
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
{
std::vector<RTLIL::State> bits = this->bits;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index ab1b9bec..e9dfa5ac 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -213,6 +213,7 @@ namespace AST
// helper functions for creating AST nodes for constants
static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);
static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);
+ static AstNode *mkconst_str(const std::string &str);
// helper function for creating sign-extended const objects
RTLIL::Const bitsAsConst(int width, bool is_signed);
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 01c9a009..f47d1785 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -1053,18 +1053,7 @@ basic_expr:
delete $1;
} |
TOK_STRING {
- std::string str = *$1;
- std::vector<RTLIL::State> data;
- data.reserve(str.size() * 8);
- for (size_t i = 0; i < str.size(); i++) {
- unsigned char ch = str[str.size() - i - 1];
- for (int j = 0; j < 8; j++) {
- data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
- ch = ch >> 1;
- }
- }
- $$ = AstNode::mkconst_bits(data, false);
- $$->str = str;
+ $$ = AstNode::mkconst_str(*$1);
delete $1;
} |
hierarchical_id attr {