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authorClifford Wolf <clifford@clifford.at>2013-11-24 17:17:21 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 17:17:21 +0100
commit609caa23b5e12547c043dc4a1827d1a531af1992 (patch)
tree297e7d5b77b28eebccc3bd8e7af318f174165744 /frontends
parent1e6836933d8b74d391f816ccdcf71c972f8b1db1 (diff)
Implemented correct handling of signed module parameters
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/ast.cc4
-rw-r--r--frontends/ast/ast.h2
-rw-r--r--frontends/ast/genrtlil.cc4
3 files changed, 7 insertions, 3 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 29093b83..6423cae2 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -792,7 +792,7 @@ AstModule::~AstModule()
}
// create a new parametric module (when needed) and return the name of the generated module
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters)
{
log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str());
@@ -826,7 +826,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
rewrite_parameter:
para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
delete child->children.at(0);
- child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, child->is_signed);
+ child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, signed_parameters.count(para_id) > 0);
hash_data.insert(hash_data.end(), child->str.begin(), child->str.end());
hash_data.push_back(0);
hash_data.insert(hash_data.end(), parameters[para_id].bits.begin(), parameters[para_id].bits.end());
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index de32a2bb..f9f47f6a 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -227,7 +227,7 @@ namespace AST
AstNode *ast;
bool nolatches, nomem2reg, mem2reg, lib, noopt;
virtual ~AstModule();
- virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
+ virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters);
virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
virtual RTLIL::Module *clone() const;
};
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e634a27a..177c1ec5 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1309,9 +1309,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (child->str.size() == 0) {
char buf[100];
snprintf(buf, 100, "$%d", ++para_counter);
+ if (child->children[0]->is_signed)
+ cell->signed_parameters.insert(buf);
cell->parameters[buf].str = child->children[0]->str;
cell->parameters[buf].bits = child->children[0]->bits;
} else {
+ if (child->children[0]->is_signed)
+ cell->signed_parameters.insert(child->str);
cell->parameters[child->str].str = child->children[0]->str;
cell->parameters[child->str].bits = child->children[0]->bits;
}