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authorClifford Wolf <clifford@clifford.at>2013-03-28 09:20:10 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-28 09:20:10 +0100
commit7bfc7b61a812e10177674def2f640d82cee49791 (patch)
treecf76a644db7174a9ea6571ad1412f0e23f933681 /frontends
parent98fcb5daa361c9de56ce75d9416d4eeffd01cc85 (diff)
Implemented proper handling of stub placeholder modules
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/ast.cc20
-rw-r--r--frontends/ast/ast.h6
-rw-r--r--frontends/verilog/verilog_frontend.cc10
3 files changed, 30 insertions, 6 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index d35ea417..091b196e 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -46,7 +46,7 @@ namespace AST {
// instanciate global variables (private API)
namespace AST_INTERNAL {
- bool flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg;
+ bool flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib;
AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope;
RTLIL::SigSpec *genRTLIL_subst_from = NULL;
@@ -679,6 +679,18 @@ static AstModule* process_module(AstNode *ast)
log("--- END OF AST DUMP ---\n");
}
+ if (flag_lib) {
+ std::vector<AstNode*> new_children;
+ for (auto child : ast->children) {
+ if (child->type == AST_WIRE && (child->is_input || child->is_output))
+ new_children.push_back(child);
+ else
+ delete child;
+ }
+ ast->children.swap(new_children);
+ ast->attributes["\\placeholder"] = AstNode::mkconst_int(0, false, 0);
+ }
+
current_module = new AstModule;
current_module->ast = NULL;
current_module->name = ast->str;
@@ -705,11 +717,12 @@ static AstModule* process_module(AstNode *ast)
current_module->nolatches = flag_nolatches;
current_module->nomem2reg = flag_nomem2reg;
current_module->mem2reg = flag_mem2reg;
+ current_module->lib = flag_lib;
return current_module;
}
// create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast, bool dump_ast_diff, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg)
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast, bool dump_ast_diff, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib)
{
current_ast = ast;
flag_dump_ast = dump_ast;
@@ -718,6 +731,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast, bool dump_
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
flag_mem2reg = mem2reg;
+ flag_lib = lib;
assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
@@ -747,6 +761,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
flag_mem2reg = mem2reg;
+ flag_lib = lib;
use_internal_line_num();
std::vector<unsigned char> hash_data;
@@ -821,6 +836,7 @@ void AstModule::update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes)
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
flag_mem2reg = mem2reg;
+ flag_lib = lib;
use_internal_line_num();
for (auto it = auto_sizes.begin(); it != auto_sizes.end(); it++) {
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index d65851ac..05b9a95c 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -189,13 +189,13 @@ namespace AST
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
- void process(RTLIL::Design *design, AstNode *ast, bool dump_ast = false, bool dump_ast_diff = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false);
+ void process(RTLIL::Design *design, AstNode *ast, bool dump_ast = false, bool dump_ast_diff = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false);
// parametric modules are supported directly by the AST library
// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
struct AstModule : RTLIL::Module {
AstNode *ast;
- bool nolatches, nomem2reg, mem2reg;
+ bool nolatches, nomem2reg, mem2reg, lib;
virtual ~AstModule();
virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
@@ -217,7 +217,7 @@ namespace AST
namespace AST_INTERNAL
{
// internal state variables
- extern bool flag_dump_ast, flag_dump_ast_diff, flag_nolatches, flag_nomem2reg, flag_mem2reg;
+ extern bool flag_dump_ast, flag_dump_ast_diff, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib;
extern AST::AstNode *current_ast, *current_ast_mod;
extern std::map<std::string, AST::AstNode*> current_scope;
extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to;
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index f4a8c79f..f9731cbc 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -89,6 +89,9 @@ struct VerilogFrontend : public Frontend {
log(" -nopp\n");
log(" do not run the pre-processor\n");
log("\n");
+ log(" -lib\n");
+ log(" only create empty placeholder modules\n");
+ log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
@@ -100,6 +103,7 @@ struct VerilogFrontend : public Frontend {
bool flag_mem2reg = false;
bool flag_ppdump = false;
bool flag_nopp = false;
+ bool flag_lib = false;
frontend_verilog_yydebug = false;
log_header("Executing Verilog-2005 frontend.\n");
@@ -144,6 +148,10 @@ struct VerilogFrontend : public Frontend {
flag_nopp = true;
continue;
}
+ if (arg == "-lib") {
+ flag_lib = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx);
@@ -173,7 +181,7 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yyparse();
frontend_verilog_yylex_destroy();
- AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg);
+ AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib);
if (!flag_nopp)
fclose(fp);